1. Field of the Invention
The invention relates to a bus among integrated circuits (ICs), and more particularly, to an enhanced structure of extensible time-sharing bus structure.
2. Description of Related Art
A conventional micro-control system essentially consists of a microprocessor, a memory and an input and output (I/O) device. As shown in FIG. 1, data transfer between the microprocessor 110 and the memory 120 (or the I/O device) is proceeded through an address bus 130, a data bus 140 and access control lines 150. A width of the address bus 130 can represent a size of memory. For example, 8 address lines indicate the most memory capacity of 256 bytes.
When the memory of the micro-control system is increased, the width of the address bus 130 is accordingly increased. For example, when the memory capacity is increased to 64 k bytes, address line number is increased to 16. Thus, in addition to increasing PCB cost, memory wiring and package cost increased, and the memory capacity of the entire system cannot be extended after designed completely, which causes the manufacture and use limits.
To overcome aforementioned problem, U.S. Pat. No. 6,493,773 granted to Daniel, et al. for a “Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems” utilizes an extensible time-sharing bus structure to send addresses and data on a same address and data bus. FIG. 2 shows the operation of the bus structure. As shown, when a control signal MC1 is at high Level and a control signal MC0 is at low level, the bus sends a high byte address AH. When the control signals MC1 and MC0 are respectively at high level, the bus sends a low byte address AL. When MC1 is at low level and MC0 is at high level, the bus sends a byte of data. A slave device combines the AH and AL to obtain 16 address lines. As such, the structure does not require extending to 16 address lines since access to an extended 16-byte memory capacity is still available.
However, for increasingly complicated applications, a memory capacity of 64 k bytes cannot meet with the requirements. For accessing a memory capacity over 64 k bytes, such a bus structure can use memory bank switch to overcome insufficient address lines. However, it requires increasing time to switch memory banks so as to reduce system performance. Further, such a bus structure can only perform memory mapping access thereon, without the capability of I/O mapping access or block burst transmission.
Therefore, it is desirable to provide an improved bus structure to mitigate and/or obviate the aforementioned problems.